1. Field of the Invention
The invention relates to arrangements for reducing parasitic capacitance in complementary metal oxide semiconductor (CMOS) devices (such as CGD between the gate and the drain or source, and CGC between the gate and source/drain contacts). More specifically, the invention relates to arrangements employing a sidewall spacer made of oxynitride to reduce parasitic capacitance and to thus increase the speed of CMOS transistors.
2. Related Art
FIG. 1 shows a conventional CMOS transistor having a source S and drain D embedded in a substrate 100 which may be made of silicon. A gate dielectric layer 102 is provided between symmetrically arranged L-shaped structures 104. A gate 108, conventionally made of polysilicon, is provided atop the dielectric layer 102. Structure 110 is a silicide layer and is conventionally made of cobalt silicide (CoSi) or nickel silicide (NiSi). On opposite sides of the gate structure 108, a stack is provided that includes:                a first oxide layer 104 (may also be nitride, or a combination of oxide and nitride),        followed by a first nitride layer 114A,        followed by a second oxide layer 112,        followed by a second nitride layer 114B, which is known as the contact etch stop layer or pre-metal dielectric (PMD) liner.        
In the finished device, the second nitride layer 114B effectively joins with first nitride layer 114A to surround oxide structure 112. Source and drain contacts (not specifically illustrated, usually made of metal (tungsten)) are provided atop outlying portions of the source drain extensions (SDEs) such as by etching through the top dielectric. The CMOS transistor of FIG. 1 may be fabricated according to well known techniques (such as those disclosed in, for example, U.S. Pat. Nos. 6,743,705 and 6,677,201 which are incorporated herein by reference).
Structure 114A has conventionally served the purpose of a spacer to help define deep source and deep drain regions (S and D, respectively), which reduces the hot carrier problem and helps to prevent overrun of source and drain given recent technology advances. In conventional CMOS devices, the practice and trend has been to use spacers 114A made of pure nitride.
However, the dielectric constant of pure nitride (that is, pure silicon nitride Si3N4) is ∈=7.5, and the nitride spacer causes parasitic capacitance (such as the total gate to source/drain capacitance CGD, and gate to source/drain contact capacitance CGC) to be undesirably high. Undesirably, higher parasitic capacitance slows the transistor's operation. Accordingly, there is a need in the art to provide a spacer that has the advantages of conventional spacer arrangements but without having their disadvantages.